The present invention relates to a semiconductor memory device having memory cells alley in which dynamic memory cells are arranged in a matrix pattern, and particularly, to a semiconductor memory device capable of replacing a defective memory cell with a redundant memory cell.
As a semiconductor memory device which is developed to include advantages of both a DRAM and an SRAM, a virtual SRAM (also referred to as VSRAM, Virtually Static Ram) is known. While a pseudo SRAM (PSRAM, Pseudo Static RAM) is provided with a memory cells array including dynamic memory cells in the same way as a DRAM, it is built in with a refresh timer, executing an internal refresh operation. Consequently, an external device connected to the virtual SRAM (for example, CPU) is able to access (reading and writing data) the virtual SRAM without being conscious of the refresh operation.
Further, in the semiconductor memory device, there is generally employed redundant technology which improves production yield of the semiconductor memory device by providing beforehand a spare memory cell called a redundant memory cell and replacing a defective memory cell, which occurred in a normal memory cell array, with this redundant memory cell. This is adopted in the virtual SRAM described above.
It should be noted that in regard to the redundant technology for the semiconductor memory device, for example, it is described in the following patent document.
Japanese Unexamined Patent Publication No. Hei8-83495 is an example of related art.
On the other hand, making further improvement of yield is desired in the semiconductor memory device. However, use of the redundant technology so as to provide simply more redundant memory cells creates a problem in terms of operating speed as described as follows.
FIG. 17 is a diagram explaining a flow of access processing in a virtual SRAM using the redundant technology. As shown in FIG. 17A, corresponding to an input to an un-illustrated chip select and an external address, an address transition signal ATD (ATD signal) inside the virtual SRAM generates, and in response to this, an external access request signal RQF is generated. When the external access request signal RQF generates, the external access execution signal ACTF is generated executing external accessing.
In this external access, execution is made in order of redundancy judgment, activation and inactivation of a word line (WL). In this redundancy judgment, it is determined whether or not an address concerned is what corresponds to a redundant memory cell replaced. If it corresponds, an address corresponding to the redundant memory cell replaced is outputted. Further, as shown in FIG. 17B, when a refresh request signal RQR generates, a refresh execution signal ACTR generates in response, and a refresh access is executed.
This refresh access, too, is executed in order of redundancy judgment, activation and inactivation of a word line (WL). Note, however, that as shown in FIG. 17C, if the external access request signal RQF generates during execution of the refresh access, upon completion of the refresh access, the external access execution signal ACTF generates to execute the external access.
It should be noted that patched sections in the diagrams show time settings for address to carry out redundancy judgment and time settings of address corresponding to the world line (WL).
An access time Tac of the virtual SRAM is generally based on the chip select and the input to the external address. But since the ATD signal is an address transition signal generating in response to the input to the chip address and the external address, it is proper to use the time of ATD signal generation as a criterion inside the virtual SRAM.
When it is shown in FIG. 17A, redundancy judgment time for the external access is included in the access time Tac. Further, when it is shown in FIG. 17C, the redundancy judgment time for refresh access and the redundancy judgment time for external access are included in the access time Tac. As a result, when it is desired to increase yield by setting up more redundant memory cells, increasing the items subject to redundancy judgment will increase time for redundancy judgment, thus extending the access time.
Especially, in case of FIG. 17C, since time for redundancy judgment twice is included in the access time Tac, the problem becomes more complicated. Further, since external accessing is carried out after completion of the refresh access, time for waiting for the completion of the refresh access is added further to prolong the access time.
As described above, there is a problem that although it is possible to improve yield by setting up more redundant memory cells in the virtual SRAM, it results in extending the access time, thus making it impossible to improve the operating speed. Further, this problem is a common problem not only relating to the virtual SRAM but also to a semiconductor memory device where memory cell arrays of memory cells of the dynamic type are arranged in the matrix pattern.